With the advent of large scale integrated circuitry, the capability is at hand to embody entire computer processors on a single semiconductor chip. Arithmetic processing, local storage functions, and I/O functions can be integrated onto a single semiconductor chip to perform four-bit, eight-bit or 16-bit operand computations. As more functions are desired to be condensed onto the same semiconductor chip, the circuit density, and therefore the power dissipation per unit area, increases dramatically. Power dissipation levels oftentimes present a barrier to further consolidation of arithmetic functions in an integrated circuit. Many attempts have been made in the prior art to improve upon the architecture and circuit topology of arithmetic processing elements in order to increase their circuit density and reduce their power dissipation per unit area when integrated on a semiconductor chip.
Fette, et al. U.S. Pat No. 3,843,876 discloses a digital adder having a high speed carry propagation line. An FET adder circuit is shown in FIG. 2 of Fette, et al. which includes an FET transfer device 19 in the carry propagation path. The carry propagation control circuit includes an exclusive OR circuit consisting of devices 40, 41, 42, 43 and 44 which serve to control the conductivity of the transfer device 19. The Fette, et al. circuit is a clocked FET circuit and requires that the carry-in node 21 and the carry-out node 25 be periodically charged through the clocking devices 24 and 22, respectively. The carry generate control circuit consists of a connection between the node 16 of the carry propagate control circuit and the device 18, so as to conditionally discharge the carry-out node 25 when the binary input values A and B are both zero. The Fette, et al. circuit cannot operate faster than the repetition rate for the clocks which charge the carry propagate line, the circuit has a relatively high component count and the circuit has a relatively great power dissipation both through the additional load devices in the circuit and the on-chip clock driving circuitry.
Parsons U.S. Pat No. 3,932,734 shows an adder embodied in CMOS devices. There is a tri-state input to the carry propagate line 110. The gate 107, which is a pair of CMOS devices, provides the tri-state connection. At a particular stage, if X equals Y, the transfer gate 108 is off. The gate 107 conducts and line 106 inputs a positive potential to carry propagate line 110 when X equals Y equals one, or alternately gate 107 inputs a negative potential to carry propagate line 110 when X equals Y equals zero. If X does not equal Y, gate 107 does not conduct. In other words it is in a high impedance state. This is the third state for a tri-state operation of the gate 107. Transfer gate 108 passes the carry-in bit from the prior stage to the next stage. The carry bit will be propagated along the carry line for successive stages during the same interval. This advance of the Parsons patent over the Fette patent improves the speed of binary parallel adder circuitry, however the power dissipation and device count per adder stage is still quite high. When it is recognized that a binary parallel adder requires at least eight stages for simple adders and oftentimes 32 stages for 32-bit processors, any savings in device count and power dissipation per adder stage becomes significant. As can be seen with reference to FIG. 2 of the Parsons patent, each stage of the binary parallel adder requires an exclusive OR circuit and an AND circuit to supply the logical inputs to Parsons' input nodes 104, 105 and 106, respectively.
FIG. 3 herein, illustrates the Parsons' circuit with the transfer gates 107 and 108 and also a suggested N channel FET embodiment for the exclusive OR circuits and NAND circuits and inverter circuits within the logic box 103. It is seen that 12 transistors with four loads are required to provide the outputs on lines 104, 105 and 106 of the logic box 103. The attached FIG. 4 simplifies the transfer gates 107 and 108 to their N channel equivalents. It is seen that the same circuit elements are required in the box 103 to provide the logic signals on lines 104, 105 and 106, as are required in FIG. 3. It should be noted that the sum circuit 80 would contain Parsons' inverter 14 of two devices, inverter 15 of two devices, transfer gate 113 of one device and transfer gate 114 of one device, for a total device count for FIG. 4 of 20 N channel FET devices.
What is needed is an FET adder circuit which can efficiently perform the carry bit propagate function between consecutive bit stages of the adder while having a reduced power dissipation per unit area, a reduced device count, and a reduced signal delay.